1. Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of high dielectric constant MIM capacitors, using copper electrodes in a damascene process, and forming alternating layers of high dielectric artificial super lattices by depositing high dielectric material by MBE, molecular beam epitaxy or ALCVD, atomic layer CVD techniques.
2. Description of Related Art
In this section a description of related Prior Art background patents follows.
U.S. Pat. No. 6,218,079 B1 entitled “Method For Metallization By Dual Damascene Process Using Photosensitive Polymer” granted Apr. 17, 2001 to Shin et al. describes a copper dual damascene process with high dielectric constant silicon nitride. A photosensitive polymer having low permittivity is used as an etch mask. Though the etch mask remains in the final structure, its low permittivity reduces parasitic capacitance effects. In this method, a photosensitive polymer pattern having a first hole with a first width is formed on a first interlayer dielectric film. A second inter-layer dielectric film is formed on the photosensitive polymer pattern. A mask pattern, having a second hole, above the first hole, with a second width larger than the first width, is formed on the second interlayer dielectric film. A wiring region is formed by dry-etching the second interlayer dielectric film using the mask pattern as an etch mask. A via hole region is formed by dry-etching the first interlayer dielectric film using the photosensitive polymer pattern as an etch mask.
U.S. Pat. No. 5,976,928 entitled “Chemical Mechanical Polishing of FERAM Capacitors” granted Nov. 2, 1999 to Kirlin et al. shows a dual damascene process with a high dielectric constant ferroelectric capacitor structure. The capacitor structure is formed by sequentially depositing a bottom electrode layer, a ferroelectric layer and a top electrode layer on a base structure, optionally with deposition of a layer of a conductive barrier material beneath the bottom electrode layer. Planarization of the capacitor precursor structure by chemical mechanical polishing yields the ferroelectric capacitor structure: a stack capacitor or trench capacitor. The process is carried out without dry etching of the electrode layers or dry etching of the ferroelectric layer, to yield ferroelectric capacitors having a very small feature size, between 0.10 and 0.20 microns.
U.S. Pat. No. 6,117,747 entitled “Integration Of MOM Capacitor Into Dual Damascene Process” granted Sep. 12, 2000 to Shao et al. describes a dual damascene and MOM process for fabricating a metal-oxide-metal capacitor. A dielectric layer is provided overlying a semiconductor substrate. A dual damascene opening in the dielectric layer is filled with copper to form a copper via underlying a copper line. A first metal layer is deposited overlying the copper line and patterned to form a bottom capacitor plate contacting the copper line. A capacitor dielectric layer is deposited overlying the bottom capacitor plate. A second metal layer is deposited overlying the capacitor dielectric layer and patterned to form a top capacitor plate to complete fabrication of a metal-oxide-metal capacitor.
U.S. Pat. No. 6,271,082 B1 entitled “Method of Fabricating A Mixed Circuit Capacitor” granted Aug. 7, 2001 to Hou et al. reveals a dual damascene and capacitor process for fabricating a capacitor for a mixed circuit application. The method involves forming a first dielectric layer, a stop layer, and a second dielectric layer on a substrate having a conductive region. A first opening is then formed in the second dielectric layer, followed by forming a second opening in the stop layer and the first dielectric layer, so that the first opening and the second opening form a dual damascene opening for exposing the conductive region. The dual damascene opening is filled with a first conductive layer, so as to form a via plug and a lower electrode of the capacitor for connecting to the conductive region. A third dielectric layer, which is located between the lower electrode and a subsequent formed upper electrode, is then formed over the substrate, so that the lower electrode and a part of the second dielectric layer adjacent to the lower electrode are completely covered by the third dielectric layer. A patterned second conductive layer is formed on a part of the third dielectric layer, whereby an upper electrode for completely covering the lower electrode is formed.
U.S. Pat. No. 6,166,423 entitled “Integrated Circuit Having A Via And A Capacitor” granted Dec. 26, 2000 to Gambino et al. describes a capacitor process for manufacturing a capacitor simultaneously while forming a dual damascene via. A first interconnect layer is formed upon a first interlevel dielectric. Openings corresponding to vias and capacitors extend through a second interlevel dielectric to the first interconnect layer. A conductor is deposited in the via openings. An insulator is deposited in the openings and on the conductor in the via openings. A trench is then etched into the upper portion of the via openings while simultaneously removing the insulator from the conductor in the via openings. A conductor is then deposited in the openings and in the trenches and chemical mechanical polishing (CMP) is used to pattern the conductor. A third interlevel dielectric is then deposited, openings are formed extending to the conductors, and third interconnect layer conductors are deposited and patterned.
As a background to the present invention, existing dielectric materials are reaching their limits due to pitch size reduction and changes in capacitor architecture. The combination of hemispherical polysilicon grains (HSG) and nitride is already showing strains at 130 nm technology, and reaching to and beyond 100 nm technology, will require new dielectrics and eventually the transition to MIM capacitor structures. Furthermore, the low cost manufacturing nature of the memory business, and the extreme reluctance to change anything that is not absolutely necessary, makes for the integration of any new technology a major challenge. Chip manufacturers are looking for capacitors that have higher dielectric constant materials to replace silicon oxynitride, beginning with the 130 nm generation, and on a larger scale at 100 nm.